The present invention relates generally to high voltage integrated circuits and more specifically to high voltage pull-up devices which may be integrated into a monolithic chip having low voltage components thereon.
There are a number of applications in which a device which can actively drive the potential of a load terminal to a high positive supply value is needed. For example, such a device could be combined with an N-channel or NPN device to create a "push-pull" or "totem pole" output driver circuit. Such driving circuits would be particularly useful in running piezo-electric relays which require that driving potentials of the order of 400 volts be switched onto either of two electrodes in the relay.
Typically, high voltage lateral transistors are formed in an N type epitaxial layer on a lightly doped P substrate. An N+ emitter (or source) is diffused into a P base in one epitaxial region, and an N type collector is diffused into the epitaxial layer at a location which is spaced laterally from the base. Unfortunately, the technique is not well suited to circuit designs in which the source (or emitter) of the transistor is at a substantially different potential than the silicon substrate on which the transistor is constructed and more than one transistor is constructed on the substrate in question. For example, when a large potential is applied between the base of a transistor (or the gate of a FET) and the substrate in an NPN transistor constructed over a P substrate, an undesired current flows between these two regions. This phenomenon is referred to as "punch-through". In a pull-up device, the base of the transistor rises to the collector potential. Hence, a large potential difference between the base of the transistor and the substrate can not be avoided in such a device.
One solution to this problem is to use a depletion mode MOSFET. Since an N-channel depletion mode MOSFET constructed over a P- substrate does not contain a second P region, the punch-through problem described above is avoided. Unfortunately, such devices suffer from inversion layer shielding problems which lead to an inability to turn the device completely off. These problems are the result of a hole inversion layer which forms underneath the MOS gate at a low gate bias. This inversion layer limits the maximum width of the depletion layer that can be induced using a slowly-varying or DC gate bias.
In principle, the inversion layer effect may be overcome by the proper choice of channel implant and depth. However, the margin for error in this regard is so small that the device is difficult to manage at high yields. Furthermore, this solution limits the range of channel dopant densities which may be used. For a given set of channel dimensions, the "on" resistance of the pull-up device is determined by this dopant density. Hence, this solution is also undesirable because it results in devices which have significantly higher resistances in the "on" state.
Broadly, it is an object of the present invention to provide an improved high voltage pull-up device which can be fabricated on a common substrate with other circuit components.
It is a further object of the present invention to provide a pull-up device which does not suffer from the above mentioned inversion layer problem.
These and other objects of the present invention will become obvious to those skilled in the art from the following detailed description of the present invention and the accompanying drawings.